This invention relates generally to ferroelectric memory cells and arrays of such cells and, more particularly, to a voltage reference for a shared sense amplifier arrangement for a one transistor, one capacitor ("1T-1C") ferroelectric memory.
In a conventional integrated circuit memory, digital data is stored in a matrix of memory cells, A large number of memory cells are typically arranged in rows and columns, and are accessed by the memory's bit and word lines. A number of reference or dummy cells are usually included in the memory, arranged in a column, and are used to generate a reference voltage. Reference or dummy cells are only needed for certain memory cells, such as 1T-1C memory cells, that are not self-referenced. The reference voltage is compared to the generated voltage of an addressed column of memory cells by a sense amplifier in order to generate valid logic levels. Usually, the reference voltage is designed to have a value halfway between the voltages generated by the charge in a memory cell representing a logic zero and a logic one.
An array 10 of memory cells 12 is shown in FIG. 1, the arrangement of memory cells being designated an "open architecture", wherein the arrangement of memory cells 12 and reference cells 14 generally corresponds to their placement on an integrated circuit layout. In the open architecture, a first half 10a of the memory array includes memory cells 12 arranged in rows and columns located at each of the intersections of word lines W.sub.0 through W.sub.N and bit lines Bit.sub.0 through Bit.sub.N. A column of reference cells 14 are also included in the first half 10a of the memory array, and are addressed through the Ref word line. A second half 10b of the memory array includes memory cells 12 arranged in rows and columns located at each of the intersections of word lines W.sub.N+1 through W.sub.2N+1, and complementary bit lines /Bit.sub.0 through /Bit.sub.N. A column of reference cells 14 are also included in the second half 10b of the memory array, and are addressed through the complementary /Ref word line. Note in array 10 that for each addressed memory cell 12, there is a corresponding single output reference cell 14. A column of sense amplifiers designated SA.sub.0 through SA.sub.N is placed between the two halves of memory array 10. Each of the sense amplifiers has a first input coupled to one of the bit lines in the first half 10a of the array, and a second input coupled to one of the complementary bit lines in the second half 10bof the array. (The outputs of the sense amplifiers and other architecture structure are not shown in FIG. 1 for clarity.) The sense amplifiers resolve into valid logic levels the voltage developed by the reference cells 14 in the first half 10a of array 10 with an addressed column of memory cells 12 in the second half 10b of array 10. Conversely, the sense amplifiers also resolve into valid logic levels the voltage developed by the reference cells 14 in the second half 10b of array 10 with an addressed column of memory cells 12 in the first half 10a of array 10.
The benefit of an open architecture such as that shown in FIG. 1 is that the memory cells 12 can be tightly packed in an integrated circuit layout, as each intersection of a word and bit line includes a memory cell 12. One disadvantage of the open architecture is that signal from one column of memory cells 12 can be capacitively coupled to another column of memory cells either through wiring capacitance or junction capacitance of the substrate. This is particularly true, for example, if all of the memory cells 12 in all columns except one are latched to a logic one, whereas the memory cells 12 in a remaining column are latched to a logic zero. The capacitive coupling of signal to the remaining column may be sufficient to cause errors in the latched data. The open architecture is thus prone to noise problems that can degrade performance.
An alternative array 20 of memory cells 12 is shown in FIG. 2, the arrangement of memory cells being designated a "folded architecture", wherein the arrangement of memory cells 12 and reference cells 14 again generally correspond to their placement on an integrated circuit layout. In the folded architecture, a single memory array 20 includes memory cells 12 arranged in rows and columns located at each of the intersections of word lines W.sub.0 through W.sub.N and complementary bit line pairs Bit.sub.0, /Bit.sub.0 through Bit.sub.N /Bit.sub.N. Two columns of the single array, and are addressed through the Ref and /Ref word lines. Note that a first column of reference cells 14 addressed by the Ref word line is associated with Bit.sub.0 through Bit.sub.N bit lines, and a second column of reference cells 14 addressed by the /Ref word line is associated with the complementary /Bit.sub.0 through /Bit.sub.N bit lines. Note also in array 20 that for each addressed memory cell 12, there is a corresponding single output reference cell 14. A column of sense amplifiers designated SA.sub.0 through SA.sub.N is placed at one end of memory array 20. Each of the sense amplifiers has a first input coupled to one of the bit lines in a bit line pair, and a second input is coupled to the other of the bit lines in the bit line pair. (The outputs of the sense amplifiers and other architecture structure are also not shown in FIG. 2 for clarity.) The sense amplifiers resolve into valid logic levels the voltage developed by the first column of reference cells 12 with an addressed column of memory cells 14 having an even word line number. Conversely, the sense amplifiers also resolve into valid logic levels the voltage developed by the second column of reference cells 14 with an addressed column of memory cells 12 having an odd word line number.
The benefit of a folded architecture such as that shown in FIG. 2 is that every other column of memory cells 12 contains complementary data and therefore the capacitive coupling and resultant noise problems are diminished. However, the memory cells 14 cannot be as tightly packed in an integrated circuit layout. Note now that each intersection of a word and bit line does not necessarily include a memory cell 12. A memory cell 12 is missing from every other intersection. The folded architecture is thus generally superior to the open architecture from a circuit performance standpoint, but is more difficult to lay out and consumes more integrated circuit die area.
Turning now to FIG. 3A a two-transistor, two capacitor ("2T-2C") ferroelectric memory cell 30 is shown including transistors M1 and M2, and ferroelectric capacitors C1 and C2. Memory cell 30 is addressed by a word line 36, complementary bit lines 32 and 34, and, unlike conventional DRAM memories, an active plate line 38. Also unlike conventional DRAM memories, memory cell 30 is non-volatile, because the data state of the memory is stored as stable complementary "polarization vectors" in capacitors C1 and C2, and not as charge that must be refreshed to maintain the cell data state. Polarization vectors are defined and described in further detail below with respect to FIGS. 3B, 4A, and 4B. The operation of a 2T-2C ferroelectric memory cell is described in further detail in U.S. Pat. No. 4,873,664 entitled "Self Restoring Ferroelectric Memory" to Eaton, Jr., which is hereby incorporated by reference. In particular, refer to FIG. 4 of Eaton, Jr. and the accompanying description. Memory cell 30 is complementary and self-referenced in that the cell state is determined by comparing the polarization vector of capacitor C1 to the polarization vector of capacitor C2. Memory cell 30 can be arranged into a matrix of columns and rows without separate reference cells. Reading from and writing to memory cell 30 are accomplished preferably by applying a pulse on plate line 38.
Ferroelectric capacitors C1 and C2 are shown separately in FIG. 3B with a corresponding polarization vector arrow, which indicates the direction of polarization of the ferroelectric dielectric in the capacitor. A voltage that is greater than a material-related "coercive voltage" polarizes a substantial number of atoms within the crystal structure of the ferroelectric dielectric material to one of two stable locations within a unit cell. The polarization of the ferroelectric capacitor remains once the voltage is removed. By convention, capacitor C1 is deemed to have an "up" polarization vector, because a voltage greater than the coercive voltage is applied to the capacitor so that the "bottom plate" of the capacitor, which is at five volts, is more positive than the "top plate" of the capacitor, which is at zero volts. The "top" and "bottom" conventions refer to the physical location of the capacitor plates in the schematic diagram of FIG. 3B. The top and bottom plates of the capacitors may not necessarily correspond to the physical location in the fabricated integrated circuit memory. Also, by convention, capacitor C2 is deemed to have a "down" polarization vector, because a voltage greater than the coercive voltage is applied to the capacitor so that the "top plate" of the capacitor, which is at five volts, is more positive than the "bottom plate" of the capacitor, which is at zero volts. The complementary polarization vectors shown in FIG. 3B would actually represent one bit of data in memory cell 30, which can be arbitrarily assigned either to a logic one or logic zero data state.
The operation of ferroelectric capacitors such as those found in memory cell 30 is further described with reference to the hysteresis FIG. 40 and corresponding voltage diagram shown in FIGS. 4A and 4B. FIG. 4A is a plot of the voltage versus charge or polarization behavior of a ferroelectric capacitor. While reference may be made to "charge" in the dielectric of the ferroelectric capacitor, it should be noted that the capacitor charge dissipates, i.e. is volatile. However hysteresis curve 40 also represents polarization, which is non-volatile. Reference is made to both aspects of charge and polarization, which generally correspond before the charge on the capacitor dissipates. Various ferroelectric materials are known in the art, such as phase III potassium nitrate, bismuth titanate and the PZT family of lead zirconate and titanate compounds, among others. Given the current state of the art, the preferred ferroelectric material is PZT. One characteristic of such ferroelectric materials is a hysteresis curve or loop 40 as shown in FIG. 4A, wherein the x-axis represents the field voltage applied to the material and the y-axis represents the polarization vector (or charge) of the ferroelectric material. The flow of current through a ferroelectric capacitor depends on the prior history of the applied voltages. A voltage waveform 47 is shown in FIG. 4B that includes two positive voltage pulses and two negative voltage pulses that are applied to one electrode of a ferroelectric capacitor in a Sawyer tower circuit arrangement, which is explained in further detail below with reference to FIG. 4C. The exact timing of the pulses is arbitrary, and can include extremely long pulse widths. Circled point numbers one through six on hysteresis curve 40 correspond to the same circled point numbers on the voltage diagram of FIG. 4B.
Turning momentarily to FIG. 4C, a Sawyer tower circuit is shown having a ferroelectric capacitor 48 in series with a conventional load capacitor 49. The size of load capacitor 49 is made large with respect to the size of ferroelectric capacitor 48 so that most of the input voltage, V.sub.IN, supplied by waveform 47, is dropped across ferroelectric capacitor 48. The output voltage, V.sub.OUT, provided by the Sawyer tower circuit, is the characteristic hysteresis curve 40 typical of certain ferroelectric materials.
Starting at a first point 41 on both the hysteresis FIG. 40 and the voltage diagram of FIG. 4B (which also corresponds to circled point number one), there is no externally-applied voltage across the ferroelectric capacitor, but there was previously an applied voltage across the ferroelectric material that left the material polarized at point 41. Applying a positive voltage across the ferroelectric material moves the operating point (i.e., the current polarization) along the hysteresis curve 40 to a second point 42. The change in polarization vector or charge is designated "P" and is labeled on the rising edge of the first voltage pulse shown in FIG. 4B and on the hysteresis curve 40 shown in FIG. 4A. The charge liberated with the change in polarization vector is referred to as the "switched charge." Next, the trailing edge of the first pulse in FIG. 4B occurs between circled numbers 2 and 3. This is typically a return-to-zero transition in the externally applied voltage. Removing such positive voltage moves the polarization along the hysteresis curve to a third point 43. The direction component of spontaneous remnant polarization within the ferroelectric material is unchanged, although there is some loss of field induced polarization, i.e. a loss in the polarization magnitude in a non-ideal ferroelectric material. The change in charge is designated "P.sub.a " and is labeled on the falling edge of the first voltage pulse shown in FIG. 4B and on the hysteresis curve 40 shown in FIG. 4A. Circled point 3 is at zero externally-applied volts and, while at zero on the horizontal (voltage) axis, has a non-zero vertical component. Ideally, this remnant polarization ought to remain indefinitely. However, in practice some relaxation may occur. This is shown in FIG. 4A. Specifically, between the third and fourth points 43 and 44 on the hysteresis curve 40, there is a "relaxation" of domains within the ferroelectric material resulting in a partial loss of polarization magnitude.
Applying a second positive voltage across the ferroelectric dielectric material moves the operating point from the fourth point 44 on the curve 40 back to the second point 42. The increase in charge is now labeled "U" and is less than the P increase produced by the first positive voltage. Removing the applied positive voltage moves the operating point to the fifth point 45 on the hysteresis curve 40, with a corresponding loss of charge labeled "U.sub.a ".
Applying a negative voltage across the ferroelectric dielectric material at the fifth point 45 on the hysteresis curve 40 moves the operating point to a sixth point 46. The change in charge and polarization is labeled "N" and is shown on the leading edge of the first negative pulse in FIG. 4B. The negative voltage reverses the polarization direction of the capacitor, resulting in the original polarization direction. Since the hysteresis curve is substantially symmetrical, removing and reapplying the negative voltage moves the operating point around the "bottom" portion of the hysteresis curve in the same manner as described above. The associated changes in charge around the loop 40 are consecutively labeled "N", "N.sub.a ", "D" and "D.sub.a " in FIG. 4B. Note that the relaxation of the loop is not shown in the bottom portion of loop 40, though it exists in a non-ideal ferroelectric material, and therefore the charge components labeled "N.sub.a ", "D" and "D.sub.a " are assumed to all be approximately equal. After the two negative voltage pulses are applied and returned to zero applied volts, the operating point is returned to the first point 41 on the hysteresis curve 40.
Turning now to FIG. 5, a 1T-1C ferroelectric memory cell 52a and array 50 are shown. FIG. 5 corresponds generally to FIG. 3 of the Eaton, Jr., patent referred to above. Ferroelectric memory cell 52a includes a single MOS transistor 56 and a single ferroelectric capacitor 58. Memory cell 52a is coupled to a bit line 66, a word line 70 and a plate line 72. Array 50 includes many other memory cells, of which representative cells 52b and 52c coupled to bit line 66, and cells 52d and 52e coupled to a complementary bit line 68, are shown. The plate and word lines have been omitted from these cells for clarity. In array 50, a "dummy" cell 54a is used, in conjunction with sense amplifier 64, to resolve the data state of an addressed memory cell such as memory cell 52a. The dummy cell includes a transistor 60 and a ferroelectric capacitor 62 in the same configuration as memory cell 52a. Similarly, a dummy cell 54b on the other side of sense amplifier 64 is used to resolve the data states of memory cells 52d and 52e. Ferroelectric capacitor 62 in memory cell 54a is sized to be about twice as large as the capacitor 58 in memory cell 52a. Also, capacitor 62 always stores the polarization representative of a logic zero. If memory cell 52a also contains a logic zero, when poled, capacitor 58 will not move as much charge for the same voltage as capacitor 62, which has twice as much capacitance, and therefore complementary bit line 68 will be driven high and bit line 66 will be driven low. If memory cell 52a contains a logic one, when poled, capacitor 58 will change polarization states, liberating a large amount of charge that is greater than the amount of charge moved by capacitor 62. Consequently bit line 66 will be driven high and complementary bit line 68 will be driven low.
Although the 2T-2C memory cell of FIG. 3A is self-referenced and requires no separate reference or dummy cells, one problem with such a cell and corresponding array is that it consumes roughly twice as much area as a 1T-1C memory array to store the same number of bits. The 1T-1C memory array of FIG. 5, while solving this problem, is difficult to manufacture as an integrated circuit. One problem is that the two-to-one ratio of the dummy cell capacitor size to a memory cell capacitor size is hard to maintain from chip to chip and from one manufacturing run to another. Another problem is that there is an inherent imbalance in the bit lines coupled to the sense amplifier 64. In 1T-1C ferroelectric memory arrays, the bit line capacitance is used to sense the charge of the coupled memory cell. In a dummy cell arrangement, one bit line is coupled to one unit of capacitance in the memory cell, whereas the complementary bit line is coupled to two units of capacitance in the dummy cell. This capacitor imbalance results in lower sensitivity in the sense amplifiers and may even result in the wrong logic signal being latched by the sense amplifier.
What is desired, therefore, is a voltage reference in a balanced array configuration for a 1T-1C ferroelectric memory that is easily manufacturable on an integrated circuit with minimum die size.